In semiconductor technology, the efficient manufacture of field effect transistors is essential. For modem applications, the demands on the quality and on the performance of transistors increases.
U.S. Pat. No. 6,458,695 discloses methods for forming dual-metal gate CMOS transistors. An n-MOS and a p-MOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the p-MOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The p-MOS gate has the higher work function.
However, it may be difficult to adjust work functions of transistors in a simple manner in conventional transistor manufacture procedures.